[Verilog_LAB2] Part6

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC

`define BUS_SIZE 2
`define SL_SIZE 10	//switch LED size
`define SEG7_WD	7

module part6(
 	input		[`SL_SIZE-1:0]		SW		,
  output  [`SL_SIZE-1:0]    LEDR  ,
  output  [`SEG7_WD-1:0]    HEX0  ,
  output  [`SEG7_WD-1:0]    HEX1   
);

assign  LEDR=SW;
wire [5:0] bin6 = SW[5:0];

reg [5:0] dec_l;
reg [3:0] dec_h;

always @ (*) begin
  if (bin6 <10) begin //dec0
    dec_l = bin6;
    dec_h = 4'd0;
  end
  else if (bin6 < 20) begin //dec 1, 0 : 10~19
    dec_l = bin6-6'd10;
    dec_h = 4'd1;
  end
  else if (bin6 < 30) begin //dec 1, 0 : 10~19
    dec_l = bin6-6'd20;
    dec_h = 4'd2;
  end
  else if (bin6 < 40) begin //dec 1, 0 : 10~19
    dec_l = bin6-6'd30;
    dec_h = 4'd3;
  end
  else if (bin6 < 50) begin //dec 1, 0 : 10~19
    dec_l = bin6-6'd40;
    dec_h = 4'd4;
  end
  else if (bin6 < 60) begin //dec 1, 0 : 10~19
    dec_l = bin6-6'd50;
    dec_h = 4'd5;
  end
  else begin
    dec_l = bin6-6'd60;
    dec_h = 4'd6;
  end
    
end 

  bcd7seg uBCD_0 (
    .B(dec_h),
    .H(HEX0)
  );
  
  bcd7seg uBCD_1 (
    .B(dec_h[3:0]),
    .H(HEX1)
  );
  
  

endmodule

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC