[Verilog_LAB2] Part5

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC

 

`define BUS_SIZE 2
`define SL_SIZE 10	//switch LED size
`define SEG7_WD	7

module part5(
 	input		[`SL_SIZE-1:0]		SW		,
//  output  [`SL_SIZE-1:0]    LEDR  ,
  output  [`SEG7_WD-1:0]    HEX0  ,
  output  [`SEG7_WD-1:0]    HEX1  ,
  output  [`SEG7_WD-1:0]    HEX2  ,
  output  [`SEG7_WD-1:0]    HEX3  ,
  output  [`SEG7_WD-1:0]    HEX4  ,
  output  [`SEG7_WD-1:0]    HEX5      
);

  wire [3:0] A;
  wire [3:0] B;
  wire      C0;
  assign C0 = SW[8];
  assign A =  SW[7:4];
  assign B =  SW[3:0];

  wire  [4:0] T0; //because A[3:0]+B[3:0]+C0
  assign T0 = {1'b0,A}+{1'b0,B}+C0; //add 1bit {1'b0,*}

  reg [4:0] Z0;
  reg       C1;

  always @(*) begin
    if (T0>9) begin
      Z0=5'd10;
      C1=1'b1;
    end
    else begin
      Z0=0;
      C1=0;
    end
  end

  wire [4:0] S0;
  wire       S1;

  assign S0 = T0-Z0 ;
  assign S1 = C1;

bcd7seg uBCD0(
  .B(S0[3:0]),
  .H(HEX0)
);

bcd7seg uBCD1(
  .B({3'b000,S1}),
  .H(HEX1)
);

bcd7seg uBlank0(
  .B(4'b1010),
  .H(HEX2)
);

bcd7seg uBlank1(
  .B(4'b1010),
  .H(HEX4)
);

bcd7seg uA(
  .B(A),
  .H(HEX5)
);

bcd7seg uB(
  .B(B),
  .H(HEX3)
);


endmodule