[Vivado] 2 bit Counter, 4x1 Mux, Clock Divider

사용프로그램 : Vivado

사용보드 : BASYS 3 

-BASYS3 보드를 선택하기위해서 VIVADO에서 보드 정보를 INSTALL해주면 되지만, 간혹 INSTALL 버튼이 없을 경우 직접 설치하면 되는데 C:\Xilinx\Vivado\(해당버전)\data\boards path에 보드 파일(링크)을 넣어주면 된다. 

 

1. 2 bit Counter

`timescale 1ns / 1ps

module Counter_2bit(
    input clk               ,
    input reset             ,
    output [1:0] o_counter   
    );

    reg [1:0] r_counter = 2'b0;
    assign o_count = r_counter;

    always @ (posedge clk, posedge reset)begin
        if (reset) begin
            r_counter <= 2'b0;
        end
        else begin
            r_counter <= r_counter +1;
        end
    end

    
endmodule

2. 4x1 Mux

`timescale 1ns / 1ps

module Mux_4x1(
    input [1:0] i_sel,
    input [3:0] i_x0,
    input [3:0] i_x1,
    input [3:0] i_x2,
    input [3:0] i_x3,
    output reg [3:0] o_y
    );

    always @ (*) begin
        case (i_sel)
            2'b00 : o_y = i_x0;
            2'b01 : o_y = i_x1;
            2'b10 : o_y = i_x2;
            2'b11 : o_y = i_x3;
            default : o_y = 4'b0;
        endcase
    end
endmodule

3. Digit Splitter

`timescale 1ns / 1ps

module DigitSplitter(
    input [13:0] i_Number,
    output [3:0] o_Dig_1,
    output [3:0] o_Dig_10,
    output [3:0] o_Dig_100,
    output [3:0] o_Dig_1000
    );

assign o_Dig_1 = i_Number %10;
assign o_Dig_10 = i_Number /10 %10; 
assign o_Dig_100 = i_Number /100 %10;
assign o_Dig_1000 = i_Number /1000 %10;

endmodule

4. Clock Divider

`timescale 1ns / 1ps

module ClockDivider(
    input  clk,
    output reg o_clk = 0
    );
    
    reg [31:0] counter = 0;
    
    always @(posedge clk) begin
        if(counter == 49999) begin
            counter <= 0;
            o_clk <= ~o_clk;
        end
        else begin
            counter <= counter +1;
        end
    end
endmodule