Kraklog

프로그램 : Quaturs Prime lite edition 18.1 사용문법 : Verilog 2001 보드 : DE1-SOC module seven_segment_cntrl ( input [2:0] inp , output reg seg_a , output reg seg_b , output reg seg_c , output reg seg_d , output reg seg_e , output reg seg_f , output reg seg_g ); always @(*) begin case (inp) //if displayed to segment, add '~' in front of 7'000_0000 for invert it. 3'b000 : {seg_a,seg_b,seg_c,seg_d,seg_e,seg..

프로그램 : Quaturs Prime lite edition 18.1 사용문법 : Verilog 2001 보드 : DE1-SOC

프로그램 : Quaturs Prime lite edition 18.1 사용문법 : Verilog 2001 보드 : DE1-SOC module tb_my_rotate(); reg rotate; reg[15:0] data ; regtmp; always @(*) begin if(rotate) begin//if rotate==1 repeat (8) begin tmp = data[15]; data = {data[14:0], tmp}; end end else begin data = data; end end initial begin rotate = 1'b0; data = 16'hFFAA; #100; rotate = 1'b1; data = 16'hFFAA; #100; end endmodule test bench만 있기..

.프로그램 : Quaturs Prime lite edition 18.1 사용문법 : Verilog 2001 module mux4 ( input [3:0] mux_in_a , input [3:0] mux_in_b , input mux_sel , output reg [3:0] mux_out ); always @(*) begin if (mux_sel) mux_out = mux_in_a; else mux_out = mux_in_b; end endmodule `timescale 1 ns/1 ns module tb_mux4(); reg [3:0] mux_in_a ; reg [3:0] mux_in_b ; reg mux_sel ; wire [3:0] mux_out ; mux4 uMux4 ( .mux_in_a(mux_i..