[Verilog_LAB3] Part3

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC

설계 목표 : D 플립 플롭  (master slave)

 

module part3 (
  input       clk,
  input [1:0] SW,
  output    LEDR
);

  reg Qm;
  reg Qs;
  always @(posedge ~clk) begin
  Qm <= SW;
  end

  always @(posedge clk) begin
  Qs <= Qm;
  end
  
  assign LEDR = ~Qs;

  
endmodule

 

module part3 (
  input       clk,
  input [1:0] SW,
  output    LEDR
);

  reg Qm;
  reg Qs;
  always @(posedge ~clk) begin
  Qm <= SW;
  end

  always @(posedge clk) begin
  Qs <= Qm;
  end
  
  assign LEDR = ~Qs;

  
endmodule

module part3 (
  input [1:0] SW,
  output    LEDR
);

  wire Qm;
  wire Qs;
  wire clk =SW[1];
  wire D = SW[0];
  
  D_latch u0 (
  .clk (~clk),
  .D(D),
  .Q(Qm)
  );
  
  D_latch u1 (
  .clk (clk),
  .D(Qm),
  .Q(Qs)
 
  );
 
	assign LEDR =Qs;
 
endmodule

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