[Verilog_LAB1] Part3

 

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC

 

목표 : 2bit 4x1 multiplexer 설계

 

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`define BUS_SIZE 2
`define SL_SIZE 10
//`define USE_GNE


module part3(SW,LEDR);
	input  [`SL_SIZE-1:0] SW;
	output [`SL_SIZE-1:0] LEDR;

  wire  [`BUS_SIZE-1:0] U;
  wire  [`BUS_SIZE-1:0] V;
  wire  [`BUS_SIZE-1:0] W;
  wire  [`BUS_SIZE-1:0] X;
  wire  [`BUS_SIZE-1:0] m;
  wire s1,s0;

  assign s1 = SW[9];
  assign s0 = SW[8];
  assign U=SW[7:6];
  assign V=SW[5:4];
  assign W=SW[3:2];
  assign X=SW[1:0];
  assign LEDR [1:0] = m;
  assign LEDR [`SL_SIZE-1:2] = 0;



`ifdef USE_GNE

genvar i;

generate
	for (i=0; i<2; i=i+1)begin : MUX_2x1
	mux_4x1 uMux_4x1(
  .U(U[i]),
  .V(V[i]),
  .W(W[i]),
  .X(X[i]),
  .s0(s0),
  .s1(s1),
  .m(m[i])
);
  end
  endgenerate
  `else
  	mux_4x1 uMux_4x1_0(
  .U(U[0]),
  .V(V[0]),
  .W(W[0]),
  .X(X[0]),
  .m(m[0]),
  .s0(s0),
  .s1(s1)
);

  	mux_4x1 uMux_4x1_1(
  .U(U[1]),
  .V(V[1]),
  .W(W[1]),
  .X(X[1]),
  .m(m[1]),
  .s0(s0),
  .s1(s1)
);
`endif
 /*	always @ (*)
	if (!s1)
		LEDR = m1;
	else
		LEDR = m2;*/
endmodule

 

module mux_4x1 (
  input [7:6] SW1,
  input [5:4] SW2,
  input [3:2] SW3,
  input [1:0] SW4,
  input SW[8],
  input s1[9],
  output  m
);
wire m1;
wire m2;

mux_2x1 uMux_2x1_s01 (
  .x(U),
  .y(V),
  .s(s0),
  .m(m1)
);

mux_2x1 uMux_2x1_s02 (
  .x(U),
  .y(V),
  .s(s0),
  .m(m2)
);

mux_2x1 uMux_2x1_s1 (
  .x(m1),
  .y(m2),
  .s(s1),
  .m(m)
);

endmodule

 

mux_2x1의 모듈은 지난 발행글에서 빌드한 2x1을 이용하였다. ( 2023.12.18 - [[Harman] 하만 반도체 설계/CPU설계] - [Verilog_LAB1] Part2 )