[Verilog_LAB2] Part1

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC

 

설계 목표 : 7Segment(HEX0, HEX1)에 SW7-4, SW3-0 의 값을 나눠서 입력시킨다.  1010~1111은 표시하지 않겠다.

`define BUS_SIZE 2
`define SL_SIZE 10	//switch LED size
`define SEG7_WD	7

module part1 (
	input	[`SL_SIZE-1:0]		SW		,
 	output  [`SL_SIZE-1:0]    	LEDR  	,
	output	[`SEG7_WD-1:0]		HEX0	,
	output	[`SEG7_WD-1:0]		HEX1	
);

  wire  [3:0] a = SW[7:4];
  wire  [3:0] b = SW[3:0];
  wire	[`SEG7_WD-1:0]		Display1;
	wire	[`SEG7_WD-1:0]		Display0;

	assign HEX1 = Display1;
	assign HEX0 = Display0;
  assign LEDR = SW;

fnd uFnd_0 (
	.C      (b),
	.Display(Display0)
);

fnd uFnd_1 (
	.C      (a),
	.Display(Display1)
);

endmodule

module fnd (
	input	 [3:0]	C,
	output reg [6:0]	Display
);


always @(*)
begin
	case (C)
	//2'b**:Display=~7'babc_defg
	//2'b**:Display=~7'b654_3210
    4'b0000 : Display = ~7'b011_1111;
    4'b0001 : Display = ~7'b000_0110;
    4'b0010 : Display = ~7'b101_1011;
    4'b0011 : Display = ~7'b100_1111;
    4'b0100 : Display = ~7'b110_0110;
    4'b0101 : Display = ~7'b110_1101;
    4'b0110 : Display = ~7'b111_1101;
    4'b0111 : Display = ~7'b010_0111;
    4'b1000 : Display = ~7'b111_1111;
    4'b1001 : Display = ~7'b110_0111;	
		default : Display = ~7'b000_0000;	
  endcase
end
endmodule

//1011110
//1111001
//0000110
//1101101