Day23. Simple UART TX,7-seg button&clock

프로그램 : Quaturs Prime lite edition 18.1

사용문법 : Verilog 2001

보드 : DE1-SOC

 

 

module simple_uart_tx (
  input           clk     ,
  input           reset_n ,
  output          tx       
);

  localparam  idle  = 0 ,
              start = 1 ,
              D0    = 2 , 
              D1    = 3 , 
              D2    = 4 , 
              D3    = 5 , 
              D4    = 6 , 
              D5    = 7 , 
              D6    = 8 , 
              D7    = 9 , 
              stop  = 10 , 
              stop_1 = 11;

reg [3:0] current_state ;
reg [3:0] next_state    ;
reg [8:0] count ;
reg       rTx ;

assign  tx=rTx;
wire    bit_clr = (count == 433);

always @ (posedge clk, negedge reset_n) begin
  if(!reset_n) count <= 9'b0;
  else if (bit_clr) count <= 9'b0;
  else count <= count + 9'b1;
end

always @(posedge clk, negedge reset_n) begin
  if (!reset_n)    current_state <= idle          ;
  else if(bit_clr) current_state <= next_state    ;
end

always @(*) begin
  case (current_state)
    start  : next_state = D0     ;
    D0     : next_state = D1     ;
    D1     : next_state = D2     ;
    D2     : next_state = D3     ;
    D3     : next_state = D4     ;
    D4     : next_state = D5     ;
    D5     : next_state = D6     ;
    D6     : next_state = D7     ;
    D7     : next_state = stop   ;
    stop   : next_state = stop_1 ;
    stop_1 : next_state = idle   ;
    default: next_state = start  ;
  endcase
end

always @(*) begin
  case (current_state)
    idle   : rTx = 1'b1 ;
    start  : rTx = 1'b0 ;
    D0     : rTx = 1'b1 ;
    D1     : rTx = 1'b0 ;
    D2     : rTx = 1'b0 ;
    D3     : rTx = 1'b1 ;
    D4     : rTx = 1'b1 ;
    D5     : rTx = 1'b0 ;
    D6     : rTx = 1'b1 ;
    D7     : rTx = 1'b0 ;
    stop   : rTx = 1'b1 ;
    stop_1 : rTx = 1'b1 ;
    default: rTx = 1'b1 ;
  endcase  
end
endmodule

module tb_simple_uart_tx ();
  reg				clk		;
	reg				reset_n	;
	wire 			tx		;

	simple_uart_tx uSimple_uart_tx(
		.clk	(clk	)	,
		.reset_n(reset_n)	,
		.tx		(tx		)	 
	);
  initial begin
    clk = 1'b0;
    forever clk = #10 ~ clk;
  end

  initial begin
    reset_n = 1'b1;
    @(negedge clk);
    @(negedge clk);
    reset_n = 1'b0;
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    reset_n = 1'b1;
  end
endmodule

2ms full wave form

reset_n

rTx Output

 

 

module seven_segment_counter (
  input   bttn    ,
  input   reset   ,
  output  seg_a   ,
  output  seg_b   ,
  output  seg_c   ,
  output  seg_d   ,
  output  seg_e   ,
  output  seg_f   ,
  output  seg_g
);
  
  reg [3:0] count = 4'd0;

  seven_segment_cntrl uSeven_segment_cntrl(
    .inp  (count),
    .seg_a(seg_a),
    .seg_b(seg_b),
    .seg_c(seg_c),
    .seg_d(seg_d),
    .seg_e(seg_e),
    .seg_f(seg_f),
    .seg_g(seg_g)
  );
always @(negedge bttn, negedge reset) begin
  if (!reset) count<=4'd0;
  else if (!bttn) count <= count + 4'd1;
end
endmodule

module tb_seven_segment_counter ();
  reg bttn,reset;
  wire  seg_a;
  wire  seg_b;
  wire  seg_c;
  wire  seg_d;
  wire  seg_e;
  wire  seg_f;
  wire  seg_g;

seven_segment_cntrl uSeven_segment_cntrl(
  .inp  (bttn ),
  .seg_a(seg_a),
  .seg_b(seg_b),
  .seg_c(seg_c),
  .seg_d(seg_d),
  .seg_e(seg_e),
  .seg_f(seg_f),
  .seg_g(seg_g)
);  

initial begin
  bttn = 1'b1;
  forever #20 bttn = ~ bttn;
end

initial begin
  reset = 1'b1;
  #20 reset = 1'b0;
  #20 reset = 1'b1; 
end
endmodule