[Verilog_LAB2] Part3

설계목표 : 4비트 전가산기 - carry와 sum을 구별해서 출력시킨다.

 

`define BUS_SIZE 2
`define SL_SIZE 10	//switch LED size
`define SEG7_WD	7

module part3(
 	input		[`SL_SIZE-1:0]		SW		,
  output  [`SL_SIZE-1:0]    LEDR  
);
  
  wire [3:0] A = SW[7:4];
  wire [3:0] B = SW[3:0];
  wire       C_i = SW[8];
  wire [3:0] S;
  wire      C_o;

 assign LEDR[4:0] = {C_o,S}; 

  f_Add_4bit uF_Add_4bit(
    .i_a   (A),
    .i_b   (B),
    .i_Cin (C_i),
    .o_Sum (S),
    .o_Crry(C_o)
    );

endmodule

`timescale 1ns / 1ps

module f_Add_4bit(
    input [3:0] i_a,i_b,
    input i_Cin,
    output [3:0] o_Sum,
    output o_Crry
    );

  wire w_carry0,w_carry1,w_carry2;

  f_Add_1bit U_FA0(
    .i_a(i_a[0]),
    .i_b(i_b[0]),
    .i_Cin(i_Cin),
    .o_Crry(w_carry0),
    .o_Sum(o_Sum[0])
  );

  f_Add_1bit U_FA1(
    .i_a(i_a[1]),
    .i_b(i_b[1]),
    .i_Cin(w_carry0),
    .o_Crry(w_carry1),
    .o_Sum(o_Sum[1])
  );

  f_Add_1bit U_FA2(
    .i_a(i_a[2]),
    .i_b(i_b[2]),
    .i_Cin(w_carry1),
    .o_Crry(w_carry2),
    .o_Sum(o_Sum[2])
  );

  f_Add_1bit U_FA3(
    .i_a(i_a[3]),
    .i_b(i_b[3]),
    .i_Cin(w_carry2),
    .o_Crry(o_Crry),
    .o_Sum(o_Sum[3])
  );
endmodule

`define MUX

module f_Add_1bit(
  input i_a,
  input i_b,
  input i_Cin,
  output  o_Sum,
  output  o_Crry
);

`ifdef MUX
  wire w_xor1;
  
  assign w_xor1 = i_a ^ i_b;
  assign o_Sum = i_Cin ^ w_xor1;
  assign o_Crry = (w_xor1) ? i_Cin : i_b;
`else
  wire w_sum0, w_carry0, w_carry1;

  h_Add uH_Add0 (
    .i_a(i_a),
    .i_b(i_b),
    .o_Sum(w_sum0),
    .o_Crry(w_carry0)
  );

  h_Add uH_Add1 (
    .i_a(w_sum0),
    .i_b(i_Cin),
    .o_Sum(o_Sum),
    .o_Crry(w_carry1)
  );

  assign o_Crry = w_carry0 | w_carry1;
`endif

endmodule

`timescale 1ns/1ps

module h_Add (
  input i_a,
  input i_b,
  output o_Sum,
  output o_Crry
);
  assign o_Sum = i_a ^ i_b; //A xor B
  assign o_Crry = i_a & i_b; // A and B
endmodule

module mux_2x1 (
  input x,
  input y,
  input s,
  output  m
);
  assign m = (~s & x)|(s&y);
endmodule

 

`define BUS_SIZE 2
`define SL_SIZE 10	//switch LED size
`define SEG7_WD	7

module part3(
 	input		[`SL_SIZE-1:0]		SW		,
  output  [`SL_SIZE-1:0]    LEDR  
);

 wire [3:0] a = SW[7:4];
 wire [3:0] b = SW[3:0];
 wire      ci = SW[8];
 wire [3:0] s;
 wire      co;

 assign LEDR[4:0] = {co,s}; 

adder_4bit uFA(
  .a (a) ,
  .b (b) ,
  .ci(ci) ,
  .s (s) ,
  .co(co)
);


endmodule

 

module adder_4bit (
  input [3:0] a,
  input [3:0] b,
  input       ci,
  output [3:0] s,
  output  co
);

  wire [3:0] c;
  assign c[0] = ci;

  FullAdder uFA0(
    .a (a[0]),
    .b (b[0]),
    .ci(c[0]),
    .s (s[0]),
    .co(c[1])
  ); 

  FullAdder uFA1(
    .a (a[1]),
    .b (b[1]),
    .ci(c[1]),
    .s (s[1]),
    .co(c[2])
  ); 
    FullAdder uFA2(
    .a (a[2]),
    .b (b[2]),
    .ci(c[2]),
    .s (s[2]),
    .co(c[3])
  ); 
    FullAdder uFA3(
    .a (a[3]),
    .b (b[3]),
    .ci(c[3]),
    .s (s[3]),
    .co(co)
  ); 
endmodule

 

`define USE_BOOL

module FullAdder(
  input   a ,
  input   b ,
  input   ci,
  output  s ,
  output  co
); 

`ifdef USE_BOOL
  wire ab_xor;
  assign ab_xor = a^b;
  assign s      = ci^ab_xor;
  assign co = (ab_xor) ? ci : b;
  //assign co = (ab_xor & ci) |(~ab_xor & b);
`else
  assign {co,s}=a+b+ci;
`endif

endmodule